The present application relates generally to an improved data processing apparatus and method and more specifically to mechanisms for clock optimization with local clock buffer control optimization.
Physical synthesis of an integrated circuit device traditionally begins with a mapped netlist. A netlist describes the connectivity of an electronic design. Netlists usually convey connectivity information and provide nothing more than instances, nets, and perhaps some attributes. Physical synthesis comprises computing an optimized netlist and corresponding layout. The objective of optimization is to meet timing constraints while minimizing area, routing congestion, and power consumption.
For efficiency reasons, physical synthesis employs heuristic approaches, starting with large changes and inexpensive analyses early in the design flow and then transitioning to more expensive analyses and restricting consideration to small changes as the design converges.